A CMOS-array-computer with on-chip communication hardware developed for massively parallel applications

Abstract

The authors present a scalable MIMD computer system which was designed to be used as neurocomputer. It is capable of emulating different types of neurons, including complex biologically motivated models based on activity pulses, variable pulse transmission times, and multiple threshold learning rules. It is constructed as an array consisting of nodal computer chips, each containing an on-chip communication processor to realize a full global communication. Hence, not only neural networks featuring arbitrary topologies can be built, but also a wide range of nonneural processing applications can be implemented. As an example, the authors show how to use the system in solving optimization problems using genetic algorithms, and how to program it for real-time image processing using a combination of neural nets, genetic algorithms, and classical image processing techniques.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>