A family of routing and communication chips based on the Mosaic

Abstract

This paper describes the specifications, internal design, and performance characteristics of the latest series of Caltech Mesh-Routing Chips (MRCs), slack-protocol-conversion chips, and router-interface chips. These highperformance, self-timed designs were derived from the corresponding parts of the message-passing system of the Mosaic (see the paper "The Design of the Caltech Mosaic C Multicomputer" in this volume), but are packaged as separate chips to allow their use by other projects engaged in the development of highly concurrent computers. In addition to n data bits, an MRC channel includes a bit to mark the tail of the packet, a self-timed request signal, and an opposite-going self-timed acknowledge signal. MRC channels operate in a queue (FIFO) discipline, in which the request and acknowledge signals provide both timing and flow control. The timing and electrical characteristics of these signals are critical to reliable communication between MRCs. The timing of the internal cha...