European Solid-State Circuits Conference · 1999 · 14 citations · 3 references
EngineeringComputer EngineeringElectrical EngineeringAnalog ElectronicsMicroelectronicsVlsi DesignAnalog Integrated CircuitsCmos Circuit DesignDigital Integrated CircuitsDigital Signal ProcessingMixed-signal Integrated Circuit DesignMixed-signal IntegrationAnalog-digital ConversionAnalog-to-digital ConversionAnalog-to-digital ConvertersArea-efficient DesignBandwidthCmos Analog Integrated CircuitsLatency EffectsPipeline Latency Optimization
A high-resolution multi-bit ΣΔ ADC architecture for operation at low oversampling ratios is introduced. An area-efficient implementation of a 3rd-order 7-bit modulator, avoiding pipeline latency effects, is presented. Clocked at 26 MHz, the 0.6µm CMOS, dual-stage ΣΔ ADC achieves 83 dB SNR over a 1.1 MHz signal bandwidth.
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