A system-level circuit model for multi- and single-chip CPUs

Abstract

This report will detail a system level circuit model that has been used to predict the performance of microprocessors, gate arrays, and mainframe computers implemented in several IC technologies. Comparisons have been made on the basis of clock frequency, power dissipation and chip/module sizes. Predictions indicate that in ten years a 0.7μm CMOS micro-processor with 6-million transistors will execute 30-60 MIPS.