A 60Gb/s 173mW receiver frontend in 65nm CMOS technology

Abstract

This paper presents a 65nm CMOS 60Gb/s receiver frontend incorporating CTLE, FFE, DFE, output slicers and clock generation as well as distribution circuits. Current-integration along with cascode gain control is used to maintain equalizer linearity under varying gain without sacrificing power consumption. Interleaved deserializing slicers achieve the high gain required for adaptive error sampling. The receiver operates error free over >1e12 bits at 60Gb/s, occupies 0.16mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , and consumes 173mW.