A 12 b 500 MSample/s current-steering CMOS D/A converter

Abstract

This 12b 500MSample/s CMOS current-steering D/A converter has a segmented architecture. The 5MSBs are converted using the unary approach. A fully custom-made thermometer decoder is manually laid out to achieve the 500MSample/s update rate. The 7LSBs are converted using the binary approach, where the digital input bits directly control the switches. To minimize latency problems and to optimize dynamic performance, a dummy decoder is inserted between the inputs and the switch transistors. Using this architecture, a trade-off between good static specifications and moderate power complexity of the DAC is achieved.