Publication | Closed Access
A 4MB on-chip L2 cache for a 90nm 1.6GHz 64b SPARC microprocessor
14
Citations
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2004
Year
Unknown Venue
System On ChipElectrical EngineeringMemory ArchitectureEngineeringNext-generation 1.6GhzXeon PhiHigh-performance ArchitectureSparc MicroprocessorComputer ArchitectureComputer EngineeringProcessor ArchitectureL2 CacheParallel ComputingTechnologyMicroelectronics4-Issue CpuOn-chip L2 CacheMulti-channel Memory Architecture
A next-generation 1.6GHz 4-issue CPU supports high-end servers and has a 4MB L2 cache. The chip uses 315M transistors in a 90nm 8M CMOS process with an area of 234mm/sup 2/.
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