Low power real time electronic neuron VLSI design using subthreshold technique

Abstract

We discuss a VLSI electronic neuron circuit that implements the Hindmarsh and Rose neuron model. Magnitude and time scaling techniques are employed for a 2 V power supply operation. A subthreshold operation technique and a single MOS resistor are used to minimize area and power consumption. Output bursts of the electronic neuron can be modulated dynamically by varying the input voltage level. The circuit is designed using a 0.25 /spl mu/m CMOS standard process, and the total power dissipation is 163.4 /spl mu/watt.