An Enhanced Access and Cycle Time Model for On-Chip Caches

Abstract

This report describes an analytical model for the access and cycle times of direct-mapped and set-associative caches. The inputs to the model are the cache size, block size, and associativity, as well as array organization and process parameters. The model gives estimates that are within 10% of Hspice results for the circuits we have chosen. Software implementing the model is available from DEC WRL. iiiii Table of Contents 1. Introduction 1 2. Obtaining and Using the Software 2 3. Cache Structure 2 4. Cache and Array Organization Parameters 3 5. Methodology 5 5.1. Equivalent Resistances 5 5.2. Gate Capacitances 6 5.3. Drain Capacitances 6 5.4. Other Parasitic Capacitances 8 5.5. Horowitz Approximation 8 6. Delay Model 9 6.1. Decoder 9 6.2. Wordlines 17 6.3. Tag Wordline 20 6.4. Bit Lines 21 6.5. Sense Amplifier 29 6.6. Comparator 31 6.7. Multiplexor Driver 34 6.8. Output Driver 36 6.9. Valid Output Driver 40 6.10. Precharge Time 40 6.11. Access and Cycle Times 42 7. Applications of...