A 7.1 GB/s low-power 3D rendering engine in 2D array-embedded memory logic CMOS

Abstract

Embedded memory logic (EML) is already studied for a possible solution to the system on a chip. Several different architectures are reported for maximal utilization of memory bandwidth between processor and memory. The one-dimensional processor and memory array has been applied to image processing or 2D graphics. Two-dimensional array architecture, however, is well matched to 3D graphic rendering application because basic primitives of 3D graphics such as triangles or rectangles have 2-dimensional spatial locality on the screen and they can be concurrently processed using a 2-dimensional array architecture. This 3D graphic rendering engine based on the 2D array embedded memory logic has 8 edge processors (EP), 64 pixel processors (PP), 64 frame buffers (FB) and 64 serial access memories (SAM) on the same chip. Its 3D operations include the Gouraud shading, alpha blending, depth comparison and double buffering.