Area and energy-efficient crosstalk avoidance codes for on-chip buses

Abstract

Capacitive crosstalk between adjacent wires in long on-chip buses significantly increases propagation delay in the deep submicron regime. A high-speed bus can be designed by eliminating crosstalk delay through bus encoding. In this paper, we present an overview of the existing coding schemes and show that they require either a large wiring overhead or complex encoder-decoder circuits. We propose a family of codes referred to as overlapping codes that reduce both overheads. We construct two codes from this family and demonstrate their superiority over existing schemes in terms of area and energy dissipation. Specifically, for a 1-cm 32-bit bus in 0.13-/spl mu/m CMOS technology, we present a 48-wire solution that has 1.98/spl times/ speed-up, 10% energy savings and requires 20% less area than shielding.