Normal Optical Flow measurement on a CMOS APS imager

Abstract

Results from a 2-D dense Normal Optical Flow measurement chip implemented in 0.5 /spl mu/m CMOS process are presented. The chip has a 92/spl times/52 array of APS pixels, occupies an area of 4.5 mm/sup 2/ and consumes 2.6 mW power. To illustrate the operation of the chip, we present the results of individual blocks and then the whole structure. We also demonstrate the feasibility of scaling the chip to higher resolutions without affecting the processing.