Silicon-Based True-Time-Delay Phased-Array Front-Ends at Ka-Band

Abstract

A high-power and a low-power fully integrated true-time-delay (TTD) phased-array receiver front-end have been developed for Ka-band applications using a 0.25- μm SiGe:C BiCMOS technology. The high-power front-end, consisting of a high-power low-noise amplifier (LNA) and an active TTD phase shifter, achieves 13.8±1.3 dB gain and a noise figure (NF) below 3.1 dB at 30 GHz. The front-end provides 17.8-ps continuous variable delay, with 3.5% normalized delay variation (NDV) over a 22-37-GHz frequency span. The low-power front-end, composed of a low-power LNA and a passive TTD phase shifter, achieves 14.8±3 dB gain and an NF below 3.2 dB at 30 GHz. The low-power front-end offers 22-ps continuous variable delay with only 5.5% NDV over a 24-40-GHz frequency span. The low-power front-end consumes 22.5-mW power and presents an overall input 1-dB compression point ( P 1 dB) and input third-order intercept point (IIP3) of -22 and -13.8 dBm, respectively. Depending on the linearity requirements, the high-power front-end can operate in dual-power modes. In the high-power (low-power) mode, the measured worst case input P 1 dB and IIP3 are -15.8 ( -18 dBm) and -9 dBm ( -12 dBm) at 30 GHz with an averaged power consumption per channel of 269 mW (111 mW) for similar TTD and gain performance. The core area of the high-power and low-power front-ends are 0.31 and 0.48 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , respectively.