Networking on chip with platform FPGAs

Abstract

This paper is concerned with networking at the chip level. Networks on chip have become a convenient focus for discussing the architecture of systems on chip, and design methodologies for such systems. One central question for such a focus concerns the extent to which it is useful or realistic just to scale down approaches used conventionally in larger-area computer networking. Here, we discuss this question, in the context of the modern Platform FPGA device as a system on chip substrate. We illustrate the discussion with two design examples of networking on chip being implemented in an unconventional way.