A 12 b accuracy 300 Msample/s update rate CMOS DAC

Abstract

Of several technology and architecture alternatives for >100 MHz >10 b DACs, CMOS current-steering DAC architectures are particularly suitable. (1) They can be designed in a standard digital CMOS technology, with evident cost and power consumption advantages in the integration with the digital circuits, and (2) They are intrinsically faster and more linear than competing architectures such as resistor-string DACs. This DAC is integrated in a standard digital 0.5 /spl mu/m CMOS technology. It has a current steering 6+2+4 segmented architecture: first, the six most significant bits (MSBs) are linearly decoded; second, the intermediate two bits are also linearly decoded, but independently from the MSBs; third, the four least significant bits are binary weighted.