Avalanche characteristics of MOS transistors

Abstract

This paper reviews the mechanisms that induce a negative resistance in MOS transistors operating in the avalanche mode. For n-channel devices, it is shown that snapback can be associated with the "body effect" of the MOS transistor. At high current levels, carrier injection by the source, turn-on of the parasitic n-p-n transistor, and excess carrier charge in the pinched channel are taken into account. Subthreshold currents may also be involved. The associated safe operating area limits are determined analytically. Induced failures in multi-cell power MOSTs are also discussed. An electrical model for the simulation of the device characteristics in the avalanche regime is suggested.