Using the reconfigurability of modern FPGAs for highly efficient PUF-based key generation

Abstract

Physically Unclonable Functions (PUFs) are a modern way to generate intrinsic keys by using the production tolerances of Integrated Circuits (ICs). In this paper we present a new method to increase the area efficiency of PUF implementations on FPGA-based SoCs. The complex system of logic and routing resources on FPGAs is analyzed for their usability as entropy sources for PUFs in this work. To maximize the resource usage, different implementations of PUFs are reconfigured on the same area of the FPGA. Each of them occupies the same logic block on an FPGA, but uses different logic and routing resources inside the block. A partial bit vector response is generated by each implementation. All of them are joined to a larger response vector that can be used to generate a cryptographic key. We present an implementation that is able to decrease the required resources to generate a PUF response with a given length by almost 98% on a Xilinx Zynq. The ARM processor system is used to control the reconfiguration of the FPGA. The key itself is exclusively generated and kept inside the FPGA part of the SoC to increase the security.