Modular partial reconfiguration in virtex FPGAs

TLDR

Modular systems on FPGAs can benefit from runtime module load/unload, yet Virtex and Spartan devices’ configuration architecture limits modular reconfiguration, confining research to theoretical or compromised models. The study compares two methods for implementing modular dynamic reconfiguration in Virtex FPGAs. The authors evaluate a simple, fast‑reconfiguration approach against a newer, area‑flexible method that permits modules to occupy arbitrary FPGA regions. The simpler method offers quick reconfiguration but restricts geometry, while the newer method, supporting arbitrary module placement, has been successfully applied in three real‑world cases.

Abstract

Modular systems implemented on Field-Programmable Gate Arrays can benefit from being able to load and unload modules at run-time, a concept that is of much interest in the research community. While dynamic partial reconfiguration is possible in Virtex series and Spartan series FPGAs, the configuration architecture of these devices is not amenable to modular reconfiguration, a limitation which has relegated research to theoretical or compromised resource allocation models. In this paper two methods for implementing modular dynamic reconfiguration in Virtex FPGAs are compared and contrasted. The first method offers simplicity and fast reconfiguration times, but limits the geometry and connectivity of the system. The second method, recently developed by the authors, enables modules to be allocated arbitrary areas of the FPGA, bridging the gap between theory and reality and unlocking the latent potential of partial reconfiguration. The later method has been demonstrated in three applications.