A Fully-Integrated +23-dBm CMOS Triple Cascode Linear Power Amplifier with Inner-Parallel Power Control Scheme

Abstract

The low oxide breakdown voltage of CMOS power transistor and low power-added efficiency (PAE) at low power levels have been major challenging issues in the implementation of high-power linear power amplifiers (PAs), especially in deep sub-micron CMOS technology. In order to alleviate these problems, a triple cascode CMOS PA with inner-parallel power control scheme is presented. The proposed PA, fully-integrated in 0.18/spl mu/m CMOS technology, delivers an output power of 23dBm with 35% PAE at 3.3V supply voltage. Since the thin-oxide transistors of the minimum feature size can be utilized as power transistors in the proposed PA, a high power gain of 19dB has been achieved even at single-stage. And PAE at an 8dB-backoff from the 1dB compression point (P/sub 1dB/) of 20dBm has been measured as high as 12%.