VLSI implementation of a 16*16 DCT

Abstract

The implementation of a 16*16 discrete cosine transform (DCT) chip using a concurrent architecture is presented. The chip is designed for real-time processing of 14.3 MHz sampled video data. The architecture and accuracy studies for finite-wordlength processing are discussed. The chip was implemented, tested, and found to be fully functional. Possible variations are presented for multipurpose (variable transform sizes, forward-backward transform) applications.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>