Integrated stereo Delta-Sigma class D amplifier

Abstract

A 2/spl times/40W (into 4/spl Omega/ with a 20V supply) integrated stereo /spl Delta//spl Sigma/ class D amplifier with 100dB SNR is realized in a 0.6 /spl mu/m CMOS process with DMOS transistors and buried Zener diodes. Feedback from power stage outputs gives 0.001% THD and 65dB PSRR. The modulator clock rate is 6MHz, but dynamically adjusted quantizer hysteresis reduces the output data rate to 450kHz, helping achieve 88% efficiency.