Stacked PMOS clamps for high voltage power supply protection

Abstract

Large PMOS FETs with multiple gates can be arranged to provide ESD protection to high voltage on-chip power supplies in submicron CMOS integrated circuits. These clamps divide the supply voltage among several gate oxides; the circuitry accompanying the large series FETs provides near-maximum gate drive during ESD for high pulsed current. Layouts are densely packed because minimum dimensions can be used and because no contact is needed between the stacked gates. The high voltage designs are extensions of the large PMOS FET ESD clamps and timed drive circuitry that are used to clamp ordinary on-chip power supply lines.