Two orders of magnitude leakage power reduction of low voltage SRAMs by row-by-row dynamic V/sub dd/ control (RRDV) scheme

Abstract

A novel SRAM scheme is proposed that can reduce the active leakage power by two orders of magnitude. In the low voltage region of less than 1 V, the VTH, V/sub TH/, is lowered to less than 0.2 V and the leakage power of memory cells becomes a dominant issue. By dynamically dropping the supply voltage of un-accessed cells row by row, the cell leakage can be reduced exponentially through the drain induced barrier lowering (DIBL) effect. Additionally, to lower the leakage from bit-line through transfer gates of memory cells, un-accessed word lines are applied with a negative voltage together with a reduced swing write technique. The basic advantage is verified by measurement and the effectiveness in future generations is discussed by simulations.