Circuit techniques for a 40Gb/s transmitter in 0.13μm CMOS

Abstract

Implemented in 0.13/spl mu/m CMOS, the 40Gb/s transmitter uses shunt-and-double-series inductive peaking and negative feedback for bandwidth enhancement and pulsed latch-based dividers and retimers for timing closure. The 38.4Gb/s 2/sup 31/-1 PRBS transmitted eye has differential voltage swing of 549mV/sub pp/, rise time of 14ps, and clock jitter of 0.65/sub rms/ and 4.9/sub pp/.