A 10b 3MSample/s CMOS cyclic ADC

Abstract

This low-power, small-area, 10 b 3 MSample/s (0.33 /spl mu/s) CMOS on-chip ADC uses an improved recursive subranging approach. A multi-path cyclic-conversion architecture, an implementation of a recursive subranging architecture, is proposed to further reduce the power by reducing the required circuit speed. As a result, this ADC achieves compatibility between the low-power and small-area requirements. For on-chip system application, a module that includes bus interface circuitry and buffer amplifiers for the reference-voltage generators is implemented in addition to the 10 b 3 MSample/s ADC.