Publication | Closed Access
A 5ns access time 64Kb ECL RAM
22
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0
References
1987
Year
Unknown Venue
Bipolar Ecl RamElectrical EngineeringEngineeringVlsi DesignCircuit DesignRow RedundancyIn-memory DatabaseComputer EngineeringComputer ArchitectureSemiconductor MemoryIntegrated CircuitsSegmented Bit LinesMicroelectronicsMemory ArchitectureMulti-channel Memory ArchitectureEcl Ram
An 8K×8 bipolar ECL RAM with segmented bit lines and Darlington drive circuits will be described. RAM uses the sharing signal line technique. Wafer process yield is obtained by use of a memory cell with deep P-well base diffusion and two row redundancy.