An analog front-end signal processor for a 64 Mb/s PRML hard-disk drive channel

Abstract

Synchronous channel designs, such as partial response maximum likelihood (PRML), are viable for high areal density on a hard-disk drive (HDD). Previously-published PRML channels include a 56 Mb/s channel design but without an on-chip programmable filter, synthesizer or servo demodulator. This 5V BiCMOS integrated circuit contains all the analog front-end functions necessary for a 64Mb/s HDD channel using a rate-8/9 code.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>