A sub-30 psec Si bipolar LSI technology

Abstract

The authors describe an extremely-high-speed bipolar LSI technology. It uses 0.8- mu m-rule polysilicon emitter-base self-aligned, shallow-junction, and trench-isolation technologies. An LCML circuit with a minimum propagation delay time of 24 ps/gate has been realized at a gate current of 2.2 mA. The maximum cutoff frequency of the transistor is 30 GHz. The key process of the high-speed transistor is the shallow-junction technology, using polysilicon double diffusion, a lightly doped 'link' base, collector ion implantation, and rapid thermal annealing. By using the lightly doped shallow 'link' region the degradation of BV/sub EBO/ and cutoff frequency can be avoided.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>