Low-power design of 90-nm SuperH/spl trade/ processor core

Abstract

A low-power SuperH/spl trade/ embedded processor core, the SH-X2, has been designed in 90-nm CMOS technology. The power consumption was reduced by using hierarchical fine-grained clock gating to reduce the power consumption of the flip-flops and clock-tree, synthesis and a layout that support implementation of the clock gating, and several-level power evaluations for RTL refinement. With this clock gating and RTL refinement, the power consumption of the clock-tree and flip-flops was reduced by 35% and 59%, including the process shrinking effects, respectively. As a result, the SH-X2 achieved 6,000 MIPS/W using a Renesas low-power process with lowered voltage. Its performance-power efficiency was 25% better than that of a 130-nm-process SH-X.