A 69 mW 10 b 80 MS/s pipelined CMOS ADC

Abstract

A 10 b 80 MHz pipelined ADC with an active area of 1.85 mm/sup 2/ is realized in a 0.18 /spl mu/m dual gate oxidation CMOS process and achieves 72.8 dBc SFDR, 57.92 dB SNR, and 9.29 ENOB for a 100 MHz input at full sampling rate. The ADC shares an amplifier between two successive pipeline stages in order to achieve a power consumption of 69 mW at 3 V.