A 4Mb DRAM with double-buffer static-column architecture

Abstract

A 4Mb CMOS DRAM organized 1Mb×4, measuring 6.35mm × 12.3mm, and operating at a typical row access time of 65ns, will be described. The design utilizes a double buffer architecture to achieve a static column access time of 25ns. Half V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dd</inf> -folded bit-lines are used with a substrate plate trench storage structure resulting in a cell size of 10.5μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .