A 27 mW CMOS fractional-N synthesizer/modulator IC

Abstract

A 1.8GHz transmitter supports a data rate of 2.5Mb/s using GFSK with BT=0.5, the same modulation method used in DECT. The architecture increases, by over an order of magnitude, the achievable data rate for the transmitter method, in which phase/frequency modulation is by dithering the divide value within a phase locked loop (PLL). This design avoids mixers and D/A converters to generate I and Q waveforms, so that simplicity and power savings are achieved. The system was built using a custom, CMOS fractional-N synthesizer that contains several key circuits. Included are an on-chip, continuous-time filter that requires no tuning or external components, a digital MASH /spl Sigma//spl delta/ converter that achieves low-power operation through pipelining, and a 64-modulus divider that supports any divide value between 32 and 63.5 in half cycle increments. Also included is a phase/frequency detector (PFD) that avoids dead-zone problems.