A CMOS scheme for 0.5 V supply voltage with pico-ampere standby current

Abstract

Recently, low-power requirements are getting stronger in VLSI designs. Since the power consumption of CMOS VLSIs quadratically depends on the supply voltage, low-voltage circuits have been exploited. If a VLSI is operated in 0.5 V-0.8 V V/sub DD/ range for low-power consumption, the threshold voltage of MOSFETs, V/sub TH/, should be well below 0.5 V to turn the MOSFETs on. V/sub TH/ between 0.1 V and 0.2 V causes 10 nA-order subthreshold leakage current per logic gate in a standby mode, which leads to 10 mA standby current for 1M-gate VLSIs. This hinders application of the VLSIs in mobile equipment powered by a small battery. The super cut-off CMOS (SCCMOS) circuit overcomes this problem. With the SCCMOS, operation is possible below 0.5 V-0.8 V V/sub DD/ with 0.1 V-0.2 V V/sub TH/ and, at the same time, pA-order standby current per logic gate can be achieved.