A 2 mW 89 dB DR continuous-time ΣΔ ADC with increased immunity to wide-band interferers

Abstract

A continuous-time /spl Sigma//spl Delta/ ADC with merged channel filter and programmable-gain functionality is presented. Interferers above full-scale can be applied without jeopardizing reception of weak desired signals. The merged design occupies 0.14 mm/sup 2/ in 0.18 /spl mu/m CMOS, consumes 2 mW, and achieves 89 dB of dynamic range (DR) in a 1 MHz bandwidth.