VHDL modeling and simulation of data scrambler and descrambler for secure data communication

Abstract

VHDL modeling and simulation of a typical data scrambler and descrambler for secure data communication has been presented. The encoder and decoder has been implemented using VHDL approach which allows the reconfigurablity of the proposed system such that the key can be changed as per the security requirements. The power consumption and space requirement is very less compared to conventional discrete I.C. design which is pre-requisite for any system designer. The design has been synthesized on EP1S0F484C5 of Straitx FPGA family. The results of the simulation have been found to be satisfactory and are in conformity with theoretical observations.