A 21-ns 32 K×8 CMOS static RAM with a selectively pumped p-well array

Abstract

The design and performance of a 32 K/spl times/8-b CMOS static RAM (SRAM) are presented. The design features a selectively pumped p-well array. Using this array technology, high-impedance polysilicon resistor loads can be used to reduce the array standby current by three orders of magnitude, and the device characteristics can be optimized to achieve high speed in the peripheral circuits. A unique divided-word-line architecture with shared sense amplifiers is used to achieve high-speed read operation. The read speed is further enhanced by a novel quasistatic equalization that minimizes peak current. A high-speed write circuit with a write-to-read transition detection is used to achieve a fast write operation. An advanced 1.2-/spl mu/m double-level-metal CMOS technology was used to fabricate the devices. The access time is 21 ns and the active power is 330 mW at 22 MHz.