A power stage optimization method for monolithic DC-DC converters

Abstract

This paper presents a detailed power loss model for a monolithic buck converter power stage in a standard CMOS process. The loss model includes power dissipation in the drivers, as well as conduction and switching losses in the power MOSFET devices. For a given set of operating conditions, the power loss model allows optimum selection of the design parameters: the gate-drive tapering factor, the gate-drive voltage swings, and the widths of the power MOSFET devices. As an example, modeling and optimization results are described for a 2-to-1 V, 200 mA converter in a standard 0.35μ CMOS process, with switching frequencies in the range from 1 MHz to 10 MHz. The modeling and optimization results are validated by detailed circuit simulations.