Extensions to Verilog-A to support compact device modeling

TLDR

The paper reviews compact modeling and analog circuit simulation, illustrating the concepts with a simple Verilog‑A capacitor model. It aims to extend Verilog‑A to better support compact device modeling. The authors propose and tentatively implement several extensions, building on the example capacitor model to demonstrate their applicability. The study concludes with a revised capacitor model that incorporates the proposed extensions.

Abstract

We discuss extensions to Verilog-A that address compact modeling needs. It reviews compact modeling and analog circuit simulation, and then presents a simple Verilog-A compact model for a capacitor. Based on this example, extensions are presented that make Verilog-A better suited to compact modeling. A tentative implementation of each extension is proposed and described. We conclude with a summary of the extensions, implemented in a revised capacitor model.