Reducing Power Consumption of the Issue Logic

Abstract

A technique to reduce the power consumption of the issue logic of superscalar processors is presented. We have evaluated the power consumption of different parts of the architecture through a detailed cycle-by-cycle simulation. The results show that one of the principal power consumption's factor in a superscalar processor is the hardware devoted to extract parallelism from applications. We propose a technique to dynamically resize the instruction queue based on the existing parallelism in different periods of the execution. With the proposed method we can save about 15 per cent on the total power consumption in the processor. 1