Low power analog neurosynapse chips for a 3-D "sugarcube" neuroprocessor

Abstract

Object discrimination and pattern recognition are computationally intensive and for many defense and commercial applications, speed is of the essence. A novel 3-dimensional VLSI architecture in which neural network integrated circuits (ICs) are stacked together and mated to an image sensor may be used to solve such problems. New compact, high speed, low power, analog neuron and synapse circuits, suitable for such 3-D z-plane stacking are reported. The neural circuits have been designed for incorporation into a reconfigurable multilayer perceptron consisting of 64 inputs, up to 64 hidden units, and up to 6 outputs, which can be utilized to solve a variety of pattern recognition problems. The circuits, fabricated in a 1.2 /spl mu/m CMOS process have achieved 125 ns propagation through a synapse neuron pair, resulting in 4 MHz operation through the envisioned 3 layer feed forward network. Power dissipation at these speeds is expected to be under 30 mW per chip.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>