A low-noise low-voltage CT ΔΣ modulator with digital compensation of excess loop delay

Abstract

The implementation of a 3/sup rd/-order 50MS/s CT /spl Delta//spl Sigma/ modulator with 5 levels of quantization, for a CDMA2k receiver, is presented. Its 9nVrms//spl radic/Hz input referred noise produces 80dB of DR in a 600kHz BW for signals as low as 70mVrms. It draws 4mA from a single 1.5V supply, uses a 90nm CMOS process and occupies 0.25mm/sup 2/.