Parallel Hardware Implementation of a Broad Class of Spiking Neurons using Serial Arithmetic

Benjamin Schrauwen, Jan M. Van Campenhout

Ghent University Academic Bibliography (Ghent University) · 2006 · 29 citations · 5 references

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Abstract

Current digital, directly mapped implementations of spiking neural networks use serial processing and parallel arithmetic. On a standard CPU, this might be the good choice, but when using a Field Programmable Gate Array (FPGA), other implementation architectures are possible. This work present a hardware implementation of a broad class of integrate and fire spiking neurons with synapse models using parallel processing and serial arithmetic. This results in very fast and compact implementations of spiking neurons on FPGA.

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