Spread-spectrum clock generator for serial ATA using fractional PLL controlled by ΔΣ modulator with level shifter

Abstract

Implemented in a 0.15/spl mu/m CMOS process, the spread-spectrum clock generator uses the fractional PLL controlled by a /spl Delta//spl Sigma/ modulator An adaptive level shifter is adopted for expanding the input range of the /spl Delta//spl Sigma/ modulator. The 1.5GHz prototype achieves the peak spurious reduction level of 20.3dB and the random jitter of 8.1 ps in a 250-cycle averaging period.