A 0.5-μm CMOS T/R switch for 900-MHz wireless applications

Abstract

A single-pole double-throw transmit/receive switch for 3.0-V applications has been fabricated in a 0.5-/spl mu/m CMOS process. An analysis shows that substrate resistances and source/drain-to-body capacitances must be lowered to decrease insertion loss. The switch exhibits a 0.7-dB insertion loss, a 17-dBm power 1-dB compression point (P/sub 1 dB/), and a 42-dB isolation at 928 MHz. The low insertion loss is achieved by optimizing the transistor widths and bias voltages, by minimizing the substrate resistances, and by dc biasing the transmit and receive nodes, which decreases the capacitances while increasing the power 1-dB compression point. The switch has adequate insertion loss, isolation, P/sub 1 dB/, and IP/sub 3/ for a number of 900-MHz ISM band applications requiring a moderate peak transmitter power level (/spl sim/15 dBm).