A 14 b 40 MSample/s pipelined ADC with DFCA

Abstract

A DAC and feedback capacitor averaging (DFCA) technique used in a pipelined ADC achieves 84 dB SFDR and 74 dB SNR. Also external mismatch noise cancellation digitally improves the SNR. Excluding output drivers, the 0.6 μm double-poly BiCMOS ADC dissipates 860 mW from 3.3 V supply.