A 200 MHz 2.5 V 4 W superscalar RISC microprocessor

Abstract

This RISC microprocessor is based on a microarchitecture designed in a 2.5 V CMOS technology. The 78.75 mm/sup 2/ design features dual 16 kB instruction and data caches, a floating-point unit, an integer unit, a branch unit, a load/store unit, and a system unit. Two instructions per cycle can be dispatched in this superscalar design. The user-configurable multiplying PLL provides a processor clock at 2/spl times/, 2.5/spl times/, 3/spl times/, 3.5/spl times/, 4/spl times/, 4.5/spl times/, 5/spl times/, 5.5/spl times/, and 6/spl times/ the bus clock frequency. Testability features include level-sensitive-scan-design (LSSD), array-built-in-self-test (ABIST) logic for cache and tag arrays, and a JTAG interface.