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A trench-isolated power BiCMOS process with complementary high performance vertical bipolars
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2003
Year
Unknown Venue
Low-power ElectronicsElectrical EngineeringPower Management ApplicationsEngineeringVlsi DesignHigh Voltage EngineeringCircuit SystemMixed-signal Integrated CircuitNew ProcessPower ElectronicsProcess ArchitectureMicroelectronics
A new process for mixed-signal and power management applications is introduced. The process architecture is designed to achieve high V/sub A/, high f/sub T/ complementary 24 V bipolar devices coupled to 0.5 /spl mu/m CMOS and 24 V power MOS. For optimum performance and die size the process uses 1 /spl mu/m wide poly-filled trench isolation.