HP's PA7100LC: a low-cost superscalar PA-RISC processor

Abstract

Describes a new low-cost, superscalar PA-RISC processor including two integer arithmetic and logic units, a floating-point coprocessor, and a memory and I/O controller on a single VLSI chip. It implements the full PA-RISC1.1 functionality and adds several new features, including little-endian capability, uncacheable memory pages, and new multimedia instructions. The chip is fabricated in 0.8- mu m, three-level metal CMOS and is designed to run from 0 to 75 MHz. The cache system consists of an off-chip combined instruction/data cache ranging from 8 kByte to 2 MByte and a small on-chip instruction buffer. Memory consists of 4 MByte to 2 GByte of standard DRAMs or SIMMs (single in-line memory modules) connecting directly to the processor chip. The chip achieves performance levels comparable to those of previous generation high-end workstations while lowering overall system cost and power consumption to make possible a new generation of low-cost systems.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>