2005 · 19 citations · 6 references
EngineeringComputer EngineeringElectrical EngineeringAnalog ElectronicsLow-power DesignMicroelectronicsAnalog Integrated CircuitsCmos Circuit DesignDigital Integrated CircuitsDigital Signal ProcessingLow-power Digital Circuit DesignMixed-signal Integrated Circuit DesignAnalog-digital ConversionAnalog-to-digital ConversionAnalog-to-digital Converter DesignAnalog-to-digital ConvertersCmos Analog Circuit DesignCmos Analog Integrated CircuitsComparator DesignPower Consumption
A third-order CT multibit /spl Delta//spl Sigma/ ADC for wireless applications is implemented in 0.13 /spl mu/m CMOS. Instead of using a 4b flash quantizer, a tracking ADC composed of 3 comparators with interpolation is used to reduce the power consumption. Over a bandwidth of 2MHz the SNR is 74dB. The ADC consumes 3mW from a 1.5V supply when clocked at 104MHz.
6
ΣΔ ADC with finite impulse response feedback DAC
B.M. Putter · 2004 · 51 citations
Engineering, Computer Engineering, Electrical Engineering +16