A 3mW 74dB SNR 2MHz CT ΔΣ ADC with a tracking-ADC-quantizer in 0.13μm CMOS

Abstract

A third-order CT multibit /spl Delta//spl Sigma/ ADC for wireless applications is implemented in 0.13 /spl mu/m CMOS. Instead of using a 4b flash quantizer, a tracking ADC composed of 3 comparators with interpolation is used to reduce the power consumption. Over a bandwidth of 2MHz the SNR is 74dB. The ADC consumes 3mW from a 1.5V supply when clocked at 104MHz.