Nacho Navarro - Concepedia

Author

Nacho Navarro

Universitat Politècnica de Catalunya

Also Known As

Conte, Tom, Nacho Navarro, Navarro, Nacho

Publications

2.3K

Citations

H-Index

Concepts

All Affiliations

Universitat Politècnica de Catalunya Barcelona Supercomputing Center University of Illinois Urbana-Champaign University of Siena Technion – Israel Institute of Technology

About

Nacho Navarro is an author at Universitat Politècnica de Catalunya specializing in engineering, computer science, and computer architecture.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	20	35	1.6K
2	Computer Science	19	33	1.5K
3	Computer Engineering	18	32	1.5K
4	Health Sciences	1	1	34
5	Management	1	1	19

Nacho Navarro

Publications

1.8K

Citations

H-Index

Page 1

	Year	Citations
Enabling preemptive multiprogramming on GPUs Ivan Tanasić, Isaac Gelado, Javier Cabezas, ACM SIGARCH Computer Architecture News EngineeringGpu BenchmarkingComputer ArchitectureGpu KernelsCompute Accelerators	2014	172
An asymmetric distributed shared memory model for heterogeneous parallel systems Isaac Gelado, John E. Stone, Javier Cabezas, ACM SIGARCH Computer Architecture News Cluster ComputingHeterogeneous ComputingEngineeringComputer ArchitectureMemory Model (Programming)	2010	164
Decomposable and responsive power models for multicore processors using performance counters Ramon Bertran, Marc González, Xavier Martorell, EngineeringEnergy EfficiencyPower Optimization (Eda)Power PhasesComputer Architecture	2010	158
An asymmetric distributed shared memory model for heterogeneous parallel systems Isaac Gelado, John E. Stone, Javier Cabezas, Cluster ComputingHeterogeneous ComputingEngineeringComputer ArchitectureMemory Model (Programming)	2010	125
Enabling preemptive multiprogramming on GPUs Ivan Tanasić, Isaac Gelado, Javier Cabezas, EngineeringGpu BenchmarkingComputer ArchitectureGpu KernelsCompute Accelerators	2014	107
DiDi: Mitigating the Performance Impact of TLB Shootdowns Using a Shared TLB Directory Carlos Villavieja, Vasileios Karakostas, Lluís Vilanova, EngineeringComputer ArchitectureMemory AccessSoftware EngineeringProcessor Architecture	2011	101
Assessing Accelerator-Based HPC Reverse Time Migration Mauricio Araya‐Polo, Javier Cabezas, Mauricio Hanzich, IEEE Transactions on Parallel and Distributed Systems Different AcceleratorsReverse Time MigrationEngineeringComputer ArchitectureSystem-level Design	2010	66
TERAFLUX: Harnessing dataflow in next generation teradevices Roberto Giorgi, Rosa M. Badía, François Bodin, Microprocessors and Microsystems EngineeringScientific Workflow SystemData ScienceHarnessing DataflowData Integration	2014	66
Thread fork/join techniques for multi-level parallelism exploitation in NUMA multiprocessors Xavier Martorell, Eduard Ayguadé, Nacho Navarro,	1999	65
Implicitly parallel programming models for thousand-core microprocessors Wen‐mei Hwu, Stephanie C. Tsao, Nacho Navarro, Proceedings - ACM IEEE Design Automation Conference Algorithm-level ParallelismEngineeringCompiler TechnologyComputer ArchitectureSoftware Engineering	2007	65

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